Design and Fpga Implementation of Ca Based Four Byte Error Detection and Correction

In certain memory systems the most common error is a single error and the next most is double error type. Here we propose a methodology and implementation of CA (cellular automata) based error correcting codes (ECCs) those are widely applied in computer memory systems. These increase reliability and data integrity. In this paper, we have proposed a novel approach for designing four byte error detecting and correcting code, based on CA concept, and implemented in VHDL. The CA already accepted as an attractive structure for VLSI implementation because of its parallelism, modularity, high performance and reliability. In this correspondence, a modular architecture of CA based (32, 28) four byte error correcting encoder and decoder has been proposed. By using cellular automata (CA) based codes,we can perform four byte error detection and four byte error correction either in check byte or in information byte.